Integrated circuit devices are typically formed on semiconductor substrates using semiconductor fabrication methods. Isolation trenches are often formed in a substrate and filled with a dielectric, e.g., shallow trench isolation (STI), to provide electrical isolation between components of an integrated circuit device. The isolation trenches are often filled using a chemical vapor deposition process, e.g., with high-density plasma (HDP) oxides. However, in the quest for smaller integrated circuit devices, spacing requirements between components often require the isolation trenches to have relatively narrow widths, resulting in large aspect (or trench-depth-to-trench-width) ratios. The large aspect ratios often cause voids to form within the dielectric while filling these trenches.
Memory device fabrication is an example where problems exist with filling large-aspect-ratio isolation trenches. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address. During fabrication, the isolation trenches are formed between successive columns of memory cells of the array and are filled with dielectrics to electrically isolate the columns from each other. As memory devices continue to become smaller in size, the spacing between the columns is reduced and thus exacerbates the problems of void formation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative trench filling processes.